Conventionally, a coprocessor module attached to a processor core (“microprocessor”) interacts directly with the processor's pipeline. This means that the coprocessor functions at the same frequency of operation as the processor. In other words, the coprocessor is able to work in lock-step with the processor and its pipeline. This duality of operating at a same frequency is achievable by having dedicated circuitry for the processor and the coprocessor being implemented in the same technology.
However, today processors are being embedded in Application Specific Integrated Circuits (“ASICs”), Application Specific Standard Products (“ASSPs”), and System-On-Chips (“SoCs”). These SOCs may be implemented in programmable logic devices, such as Field Programmable Gate Arrays (“FPGAs”) that may contain one or more embedded microprocessors. As an example, such embedded microprocessors may be integer-only processors with floating-point support provided by software emulation. However, floating-point support via software emulation being run on an embedded processor ties up the processor, and thus does not have the advantage of off-loading floating-point tasks to a coprocessor.
Alternatively, a floating-point coprocessor unit (“FPU”) may be implemented in the FPGA fabric along with the embedded processor. For example, a PowerPC processor core from International Business Machines Corporation (“IBM”), White Plains, N.Y., may be embedded in an integrated circuit along with a FPU core from QinetiQ Ltd. (“QinetiQ”), Worcestershire, United Kingdom. However, such an FPU core conventionally operates at less than one third of the maximum operating frequency of the PowerPC processor core, and thus processor performance is slowed for operating the coprocessor. More details regarding a PowerPC processor core may be found in a publication entitled “Enhanced PowerPC Architecture” version 1.0 dated May 7, 2002 from IBM, which is incorporated by reference herein in its entirety. Additionally, more details regarding an FPU core from QinetiQ may be found in “Quixilica® Floating-Point Unit For PPC405 Core with Optimised Vector Maths Library” by QinetiQ, [online] (Jul. 16, 2004)<<URL:http://www.quixilica.com/products_qxfpu.htm and URL:http://www.qinetiq.com/home/markets/information_communicati on_and_electronics/digital_signal_processing/quixilica_download s.html>.
Notably, it may not be practical to provide an embedded coprocessor along with an embedded processor in an integrated circuit due to having to slow performance of the embedded processor to operate the coprocessor. Moreover, designing a coprocessor core to operate at the relatively high frequencies of a processor core is at best problematic and subject to functional limitation or obsolescence if the instruction set of the processor core is subsequently altered. Furthermore, with respect to FPGAs, it may not be desirable to consume semiconductor die area for an embedded coprocessor at the expense of reconfigurable resources.
Accordingly, it would be desirable and useful to provide means for operating a coprocessor at a frequency slower than the frequency of operation of a processor with less performance impact on the processor as compared with slowing the processor to operate at the coprocessor speed or emulating the coprocessor operations on the processor.